Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Research Fellow: Sheng-Hong Wang

Advisor: Jose Renau


There is a resurgence in hardware accelerators due to power and performance constraints. At the same time, there is a resurgence in new Hardware Description Languages (HDLs). Many researchers see Verilog as the equivalent to the assembly in hardware specification, and they are creating new Hardware Description Languages to increase the abstraction. The goal of this proposal is to build a Multi-Language Synthesis and Simulation Infrastructure (MLSSI). MLSSI is the equivalent of a compiler infrastructure but for synthesizable languages like CHISEL, synthesizable Verilog, and Pyrope.

LiveHD is an infrastructure designed for Live Hardware Development. By live, we mean that small changes in the design should have the synthesis and simulation results in a few seconds, as the fast interactive systems usually response in sub-second.

As the goal of "seconds," we do not need to perform too fine grain incremental work. Notice that this is a different goal from having a typical incremental synthesis, where many edges are added and removed in the order of thousands of nodes/edges.




Live techniques



See Also