LGraph: Open Source Multi-Language Synthesis and Simulation Infrastructure

Research Fellow: Sheng Hong Wang

Advisor: Jose Renau


There is a resurgence in hardware accelerators due to power and performance constraints. At the same time, there is a resurgence in new Hardware Description Languages (HDLs). Many researchers see Verilog as the equivalent to the assembly in hardware specification, and they are creating new Hardware Description Languages to increase the abstraction. The goal of this proposal is to build a Multi-Language Synthesis and Simulation Infrastructure (MLSSI). MLSSI is the equivalent of a compiler infrastructure but for synthesizable languages like CHISEL, synthesizable Verilog, and Pyrope.

LGraph is a graph optimized for live synthesis (Live Synthesizes Graph or LGraph for short). By live, we mean that small changes in the design should have results in a few seconds. The goal is that any code change can have its synthesis and simulation setup ready under 30 seconds with a goal of under 4 seconds in most cases.



 [1] R. T. Possignolo, S. H. Wang and J. Renau, “LGraph: A multi-language open-source database for VLSI,” in WOSET’18.

 [2] R. T. Possignolo and J. Renau, “LiveSynth: Towards an interactive synthesis flow,” in DAC’17.

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